RLDRAM

A single 32 MByte RLDRAM and its controller has enough throughput to support many PEs possibly up to 20 if some wait states are accepted. Bank collisions are mostly avoided by the MMU hashing policy. There are several Virtex-II-Pro boards with RLDRAM on board which can clock the RLDRAM at 300 MHz with DDR I/O, well below the 400 MHz specification, but the access latency is still 20 ns or 8 clocks.